This invention relates to a semiconductor device having a multilayer structure (hereinafter referred to as xe2x80x9ca stack structurexe2x80x9d) and attaining high integration density, particularly, to a semiconductor device wherein the aspect ratio of a contact hole or the like, which electrically connects the stacked layers in the stack structure can be reduced, thereby can be highly integrated, and the manufacturing method thereof.
The integration density of the semiconductor device such as a DRAM (Dynamic Random Access Memory) which requires to be highly integrated is increased by reducing the design rule. To form such a device, the self-alignment technique is widely employed, with which fine devices can be formed, irrelevant to the precision in the mask-alignment in the photolithography process.
The self-alignment technique is classified into various types. SAC, the self-alignment contact is one of the self-alignment techniques, which is necessary to form a 256M DRAM. With use of the SAC, contact holes are formed on the surface of the semiconductor layer, as designed. The SAC is a technique for obtaining a desired etching selectivity by forming an etching stopper on a gate electrode before forming an interlayer insulating film, thereby improving the margin to compensate the alignment error in the photolithography process.
FIGS. 1A-1H show the steps of the manufacturing process of the 256M DRAM, in accordance with the present POR (Process Of Record).
As shown in FIG. 1A, a thin gate oxide film 2 is formed on a silicon substrate 1, at first. Then, as shown in FIG. 1B, material of a gate electrode, i.e., a polycrystalline silicon (hereinafter referred to as xe2x80x9cpoly-Sixe2x80x9d) layer 3 of 100 nm thick and a tungsten silicon (hereinafter referred to as xe2x80x9cWSixe2x80x9d) layer 4 of 55 nm thick are stacked on the gate oxide film 2, and a silicon nitride (SiN) layer 5 having a 160 nm thickness as an insulating gate cap layer is further stacked thereon by the CVD technique.
Thereafter, by the photolithography technique and the RIE (Reactive Ion Etching), for example, the SiN layer 5, the WSi layer 4, and the poly-Si layer 3 are etched selectively at a portion so as to expose the gate oxide film 2, as shown in FIG. 1C, thereby a gate electrode is obtained. Subsequently, a post oxide film (not shown) is formed on side walls of the WSi layer 4 and the poly-Si layer 3 by the thermal oxidation technique or the like. Next, impurity such as arsenic is implanted in the silicon substrate 1 by the ion implantation technique, for example, through the gate oxide film 2 in order to form a drain (or source) diffusion layer 6 on the surface of the silicon substrate 1.
Subsequently, a SiN layer 7 having a 40 nm thickness is deposited as an etching stopper on the SiN layer 5 or side walls of the SiN layer 5, the WSi layer 4 and the poly-Si layer 3, and the gate oxide film 2 by the CVD technique, as shown in FIG. 1D. Then, a SiO2 layer 8 as an interlayer insulating film is deposited on the SiN layer 7, as shown in FIG. 1E.
In this time, as shown in FIG. 1F, a photoresist layer 9 having a contact hole region is formed above the gate electrode by selectively depositing photoresist at a position substantially corresponding to that of the gate electrode. By depositing the photoresist in this manner, the contact hole region can be surely located in the photoresist layer 9, even if the photoresist layer 9 is formed to shift a little from a desired position.
Thereafter, the SiO2 layer 8 exposed at the bottom of the opening portion of the contact hole region in the photoresist layer 9 is removed by the RIE technique, as shown in FIG. 1G. In this time, the SiN layer 7 is also etched at the upper corners of the gate electrode, with the SiN layer 5 also etched by about 10 nm at the upper corners.
After etching the SiO2 layer 8, the SiN film 7 exist at the bottom of the contact hole region is etched by the RIE technique, as shown in FIG. 1H. In this time, the SiN layer 5 is also etched by about 100 nm to leave the 50 nm thick SiN layer above the gate oxide film 2 at the ends of the gate electrode.
Then, the exposed portion of the gate oxide film 2 and the photoresist layer 9 are removed, and a drain (or source) electrode is formed to contact with the surface of the exposed portion of the silicon substrate 1. In this manner, a MOS transistor applicable to a DRAM is obtained. A capacitor suitable to the desired type of the DRAM is then formed, and the desired DRAM is obtained.
The thickness of 50 nm of the SiN layer 5 located at the corners of the gate electrode shown in FIG. 1H, is the minimum thickness for preventing the leakage current which may flow from the conductive electrode filling the contact hole to the gate electrode. The minimum thickness is 50 nm now although the minimum thickness may be reduced to almost 20 nm in the device in the next generation.
As described above, in order to leave the 50 nm thick SiN layer after etching the SiO2 layer 8 and the SiN film 7, a 160 nm thick SiN layer 5 needs to be formed at first.
Such a thick SiN layer 5, however, will increase the aspect ratio of the contact hole region arranged between the gate electrodes having a multilayer structure (hereinafter referred to also as xe2x80x9cgate stackxe2x80x9d), which makes it difficult to fill the contact hole with the SiO2 layer 8 and to etch the SiO2 layer 8.
Accordingly, the gate stack needs to be formed thin in height in view of the reduction of the aspect ratio of the contact hole region and the integration density of such a device required to be so highly integrated as the 256M DRAM or the device in the next generation, which has a finer pattern than the 256M DRAM.
In order to obtain such a thin gate stack, however, the filled oxide (the SiO2 layer 8) needs to be etched with remarkably high etching selectivity in comparing with that of the nitride at the upper corners of the gate stack.
The object of the present invention is to provide a semiconductor device capable of increasing the etching selectivity and reducing the aspect ratio of the contact hole arranged between multilayered elements, thereby increasing the integration density, and the manufacturing method thereof.
The present invention is mainly characterized in that multilayered elements and the element to be etched are located on the same substrate, and the element to be etched is etched with high etching selectivity by exposing an etching stopper layer which is exist in the multilayered elements and has a low etching rate.
Further, according to the present invention, the thickness of the etching stopper can be reduced by forming the etching stopper to reduce the etching rate thereof, and thus the total thickness of the multilayered elements can be reduced, as a result. The self-alignment technique is not always essential to obtain the object of the present invention, but preferable to be employed in view of the improvement of the reliability. When the present invention is applied to a DRAM, the aspect ratio of the contact hole arranged between the gate stacks can be reduced, thereby the DRAM can obtain high integration density. Needless to say, it is understood that the present invention can be applied not only to the DRAM, but also the other device having such a multilayered structure.
In order to obtain the object of the present invention, the semiconductor device of the present invention is constituted as described below.
According to the first aspect of the present invention, the semiconductor device of the present invention comprises: a substrate; a gate insulating film selectively formed on the substrate; a gate electrode formed on the gate insulating film; a gate cap layer formed on the gate electrode; a protective insulating film (etching stopper) formed on the gate cap layer and side walls of the gate electrode; and a source and drain diffusion layer formed on the surface of the substrate to be contact with a channel forming region formed below the gate electrode.
According to the second aspect of the present invention, the manufacturing method of the semiconductor device of the present invention comprises the steps of: forming a gate electrode on a gate insulating film selectively formed on a substrate; forming a gate cap layer on the gate electrode; forming a diffusion layer at the substrate with use of the gate cap layer as a mask; forming a protective insulating film on the substrate so as to cover the gate cap layer and the gate electrode; forming an interlayer insulating film on the protective insulating film; forming an opening to be aligned with the gate electrode in a self-aligned manner by etching a part of the interlayer insulating film and a part of the protective insulating film in order to expose the surface of the substrate at the bottom of the opening; and forming a wiring layer electrically connected to the exposed surface of the substrate.
According to the first and second aspects of the present invention, the gate cap layer and/or the protective insulating film comprise a plurality of materials which are different from each other and stacked on each other.
More specifically, the protective insulating film may comprise a nitride layer formed on the gate cap layer and the side wall of the gate electrode, and a silicon layer formed on the nitride layer.
Similarly, the gate cap layer may comprise a nitride layer formed on the gate electrode, and an oxide layer formed on the nitride layer.
With the above-mentioned constitution, the present invention has the following effects and advantages;
According to the present invention, when the protective insulating film has the multilayered structure, the insulating layer having a lower etching rate than that of the interlayer insulating layer can be exposed during the etching of the interlayer insulating layer. The exposed insulating layer with the lower etching rate protects the gate stack from the etching, and the gate stack can be formed thin and the aspect ratio of the contact hole can be reduced. The reduction of the aspect ratio of the contact hole enables the integration density of the device increase.
When the gate cap layer has the multilayered structure, the insulating layer having a lower etching rate than that of the protective insulating layer can be exposed during the etching of the protective insulating layer at the bottom of the opening. The exposed insulating film protects the gate stack similarly to the above-mentioned case, and thus the gate stack can be formed thin, and the aspect ratio of the contact hole can be reduced. The reduction of the aspect ratio increases the integration density of the device, as described before.
When both of the protective insulating film and the gate cap layer have the multilayered structure, both have the above-mentioned advantages, and thus the gate stack can be formed thinner than those of the above-mentioned cases. The aspect ratio of the contact hole can be reduced more than the above-mentioned cases, and thus the integration density can be increased more.
Additional objects and advantages of the present invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the present invention.
The objects and advantages of the present invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out in the appended claims.